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Asynchronous message passing on a dual processor parallel system running a RTOS
University of Skövde, Department of Computer Science.
1998 (English)Independent thesis Basic level (degree of Bachelor)Student thesis
Abstract [en]

Interprocessor communication is a vital part of any multiprocessor system. This work focuses on integration of an asynchronous message passing mechanism and a message notification support in the form of limited hardware queues. To fulfill requirements the interprocessor communication must be predictable, efficient, maintain memory integrity, and use the semantics of the available message passing mechanism. Various solution possibilities are identified, evaluated and compared, resulting in a design recommendation. The design uses memory restriction to build a firewall between the processors, using pointers to avoid message copying. The message queue is in the form of an array ring that can piggyback acknowledgement information. The design is general and applicable by a real-time operating systems using asynchronous message passing with explicit buffering, and has hardware support in the form of limited interrupt generating queues.

Place, publisher, year, edition, pages
Skövde: Institutionen för datavetenskap , 1998. , 37 p.
National Category
Information Science
Identifiers
URN: urn:nbn:se:his:diva-168OAI: oai:DiVA.org:his-168DiVA: diva2:2517
Presentation
(English)
Uppsok
Social and Behavioural Science, Law
Supervisors
Available from: 2007-10-12 Created: 2007-10-12 Last updated: 2009-11-25

Open Access in DiVA

fulltext(947 kB)291 downloads
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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf