Interprocessor communication is a vital part of any multiprocessor system. This work focuses on integration of an asynchronous message passing mechanism and a message notification support in the form of limited hardware queues. To fulfill requirements the interprocessor communication must be predictable, efficient, maintain memory integrity, and use the semantics of the available message passing mechanism. Various solution possibilities are identified, evaluated and compared, resulting in a design recommendation. The design uses memory restriction to build a firewall between the processors, using pointers to avoid message copying. The message queue is in the form of an array ring that can piggyback acknowledgement information. The design is general and applicable by a real-time operating systems using asynchronous message passing with explicit buffering, and has hardware support in the form of limited interrupt generating queues.